Voltage regulator has been applied in various electronic products to serve as power supply for providing stable supply voltage. However, spike will be generated on the output voltage of voltage regulator in load transient resulted from instant load change, and large voltage spike may damage the load on the voltage regulator. FIG. 1 shows waveform 100 of the output voltage of a conventional voltage regulator in load transient. At time T1, the load on the voltage regulator changes from light to heavy, and the output voltage of the voltage regulator drops down ΔV instantly, and then recovers to the original level gradually. At time T2, the load on the voltage regulator changes from heavy back to light, the output voltage of the voltage regulator jumps up ΔV instantly, and then recovers to the original level gradually. Therefore, the output voltage of a conventional voltage regulator changes with 2ΔV in load transient. To improve the ripple of output voltage generated in load transient, large output capacitor is required, and this will increase the size and cost of the voltage regulator. Alternatively, Intel proposed an adaptive voltage position (AVP) control, which uses voltage droop to reduce the output voltage spike of voltage regulator. FIG. 2 shows a conventional current mode voltage regulator 200 having voltage droop function, in which switches SW1 and SW2 are coupled between input voltage PVDD and ground GND, signals UG and LG switch the switches SW1 and SW2 to produce inductor current IL flowing through inductor L to charge output capacitor C to thereby produce output voltage Vout, error amplifier 202 generates error signal COMP from the difference between the output voltage Vout and reference voltage Vref, transconductive amplifier 212 serves as current sense circuit whose two inputs are coupled to the two ends of sense resistor Rs coupled in series to the inductor L to sense the inductor current IL to thereby generate current sense signal VCS, pulse width modulation (PWM) comparator 204 compares the error signal COMP with the current sense signal VCS to generate PWM signal for the reset input R of SR latch 206, fixed-frequency clock CLK is provided for the set input S of the SR latch 206, and the SR latch 206 produces the signals UG and LG by its outputs Q and QN to switch the switches SW1 and SW2 with drivers 208 and 210, respectively.
FIG. 3 shows waveforms of the load current IRL and output voltage Vout of the voltage regulator 200 in load transient, in which waveform 214 represents the load current IRL, and waveform 216 represents the output voltage Vout. Referring to FIGS. 2 and 3, the load RL on the voltage regulator 200 changes from light to heavy at time T1, the load current IRL increases eventually, and the output voltage Vout drops down with the voltage dropΔV=IRL×Resr  [EQ-1]where Resr is the parasitic resistor of the output capacitor C. Assuming that the error amplifier 202 has gain M, and the transconductive amplifier 212 has gain K, the output voltage Vout will drop down to the level
                              Vout          ′                =                  Vout          -                      IRL            ×            Resr            ×                                          K                M                            .                                                          [                  EQ          ⁢                      -                    ⁢          2                ]            After the output voltage Vout drops down, it will maintain at the lower level Vout′ until the load RL changes from heavy back to light at time T2, and then the output voltage Vout recovers back to the original level. By comparing FIG. 3 with FIG. 1, it is shown that the ripple of the output voltage Vout of the voltage regulator 200 in load transient is less than 2ΔV. In other words, a voltage regulator having voltage droop function may reduce the ripple of the output voltage significantly. Therefore, the voltage regulator may use smaller output capacitor C.
However, this method is only applicable for high gain voltage regulator. If the voltage regulator 200 is a low gain voltage regulator, it will not be able to reduce the ripple effect resulted from the error signal COMP and current sense signal VCS owing to the error amplifier 202 having not enough gain M, resulting in offset on the output voltage Vout. FIG. 4 shows waveforms of the error signal COMP and current sense signal VCS when the gain M of the error amplifier 202 is not large enough. When the switch SW1 turns on, the current sense signal VCS increases, as shown by waveform 302, and the error signal COMP decreases, as shown by waveform 300. Once the current sense signal VCS equal to the error signal COMP, the switch SW1 turns off, and the output voltage Vout begins to decrease, causing the error signal COMP to increase, and the current sense signal VCS to decrease. If the touch point of the error signal COMP and current sense signal VCS is not present when the load RL is zero, the output voltage Vout will have an offset apart from the reference voltage Vref in the magnitude of
                                                                           Voffset                =                                ⁢                                                      Δ                    ⁢                                                                                  ⁢                    V                    ⁢                                                                                  ⁢                    1                                    +                                      Δ                    ⁢                                                                                  ⁢                    V                    ⁢                                                                                  ⁢                    2                                                                                                                          =                                ⁢                                                      1                    2                                    ⁢                                      (                                                                  Δ                        ⁢                                                                                                  ⁢                        IL                        ×                        Resr                        ×                        M                                            +                                              Δ                        ⁢                                                                                                  ⁢                        IL                        ×                        Rs                        ×                        K                                                              )                                                                                                                          =                                ⁢                                                      1                    2                                    ⁡                                      [                                                                                            PVDD                          -                          Vout                                                L                                            ×                      Ton                      ×                                              (                                                                              Resr                            ×                            M                                                    +                                                      Rs                            ×                            K                                                                          )                                                              ]                                                                                                                          =                                ⁢                                                      1                    2                                    [                                                                                    PVDD                        -                        Vout                                            L                                        ×                                          Vout                      PVDD                                        ×                    T                    ×                                          (                                                                        Resr                          ×                          M                                                +                                                                                                                                                                                                                              ⁢                                          Rs                      ×                      K                                        )                                    ]                                ,                                                                          [                      EQ            ⁢                          -                        ⁢            3                    ]                    where ΔV1 is the amplitude of the error signal COMP, ΔV2 is the amplitude of the current sense signal VCS, ΔIL is the variation of the inductor current IL, Ton is the on-time of the switch SW1, and T is the switch period of the switches SW1 and SW2. Since L, T, Resr, Rs, M and K are all constant, from the equation EQ-3 it is obtained
                    Voffset        ∝                              (                          PVDD              -              Vout                        )                    ×                                    Vout              PVDD                        .                                              [                  EQ          ⁢                      -                    ⁢          4                ]            
The offset Voffset will result in the output voltage Vout not equal to the reference voltage Vref when the inductor current IL is zero. The equation EQ-4 shows that the variable parameters related to the offset Voffset comprise the input voltage PVDD and output voltage Vout, and it is therefore difficult to implement the equation EQ-3 by circuit to eliminate the ripple effect resulted from the error signal COMP and current sense signal VCS.
Therefore, it is desired a control method and apparatus to eliminate the ripple effect resulted from the error signal and current sense signal for a voltage regulator.